2. Computer Architecture

Pipelining — Quiz

Test your understanding of pipelining with 5 practice questions.

Practice Questions

Question 1

Which of the following pipeline hazards is characterized by a conflict over the use of a hardware resource, such as two instructions attempting to use the same ALU at the same time?

Question 2

Consider a 5-stage pipeline (IF, ID, EX, MEM, WB). If an instruction in the EX stage requires the result of an instruction currently in the ID stage, which of the following best describes the most efficient hazard resolution technique?

Question 3

A processor has a 4-stage pipeline, and each stage takes $2$ ns. If the pipeline is perfectly balanced and there are no hazards, what is the maximum theoretical instruction throughput of this pipeline in instructions per second (IPS)?

Question 4

Which of the following pipeline optimization techniques involves predicting the outcome of a conditional branch instruction to speculatively fetch instructions, and then correcting if the prediction is wrong?

Question 5

Consider a scenario where two instructions, $I_1$ and $I_2$, are in a pipeline. $I_1$ is a $LOAD$ instruction that writes to register $R_1$, and $I_2$ is an $ADD$ instruction that reads from $R_1$. If $I_2$ attempts to read $R_1$ before $I_1$ has completed its memory access and written to $R_1$, what type of data hazard occurs, and what is the relationship between $I_1$ and $I_2$?