2. Computer Architecture

Processor Datapath — Quiz

Test your understanding of processor datapath with 5 practice questions.

Practice Questions

Question 1

Which of the following describes the primary role of the 'Branch' control signal in a processor datapath?

Question 2

In a multicycle processor, what is the main reason for using separate functional units for instruction fetch, decode, execute, memory access, and write-back stages?

Question 3

Consider an ALU that performs a bitwise XOR operation on two 8-bit binary numbers: $A = 11001100_2$ and $B = 10101010_2$. What is the resulting output?

Question 4

What is the primary function of the 'MemWrite' control signal in a processor datapath?

Question 5

In a single-cycle processor, if the critical path delay is determined by the memory access time of $10 \text{ ns}$, ALU operation time of $5 \text{ ns}$, and register file access time of $3 \text{ ns}$, what is the minimum clock cycle time required for the processor?