Question 1
Which parameter quantifies the ability of a logic gate to drive multiple inputs of other gates without degrading its output logic levels?
Question 2
When interfacing a TTL output to a CMOS input, why is a pull-up resistor often necessary?
Question 3
What is the primary concern when dealing with 'ground bounce' in digital circuits?
Question 4
Which of the following describes the 'setup time' requirement for a flip-flop?
Question 5
What is the main advantage of using CMOS logic gates over TTL logic gates in terms of power dissipation?
